Field Programmable Gate Array Implementation and Testing of a Minimum-phase Finite Impulse Response Filter

The present paper depicts a prototype developed to test and verify functioning of digital filters easily. The minimumphase Finite Impulse Response (FIR) filter was a target-filter to develop such a system. The experimental setup was technologically advanced in such a way that, it compares the magnitude and phase responses of a filter; shown by Frequency Visualization tool (fvtool) of the MATLAB software with the same filter responses observed on a Digital Storage Oscilloscope in real-time operations. For this research work, an important facility provided in the MATLAB software to generating Hardware Description Language (HDL) for a given filter objects was deployed. A Very High Speed Integrated Circuit HDL (VHDL) soft Intellectual Property (IP) core was generated for the minimum-phase FIR filter, and instantiated it in a top level entity, along with a clock divider VHDL module; capable of providing proper sampling clock to the filter. For implementation of this core, the Xilinx Field Programmable Gate Array (FPGA) Virtex-5 device was deployed. Around this reconfigurable device, there was an Advanced RISC Machine (ARM) microcontroller, to provide inter-conversion between Analogue and Digital signals; essential for the filter testing. Keywords-FPGA; minimum-phase FIR filter; MATLAB; fvtool; ARM microcontroller